This functionality is being developed in the current ESA UVVM project and has so far not been mentioned in any previous UVVM presentation.Įspen Tallaksen CEO, Co-founder and Principal FPGA designer at EmLogic, the new and rapidly growing Norwegian Embedded Systems & FPGA Design Centre. This presentation will briefly mention these benefits but will focus on brand new functionality to be released very soon. UVVM is making this much easier through the provided Testbench Infrastructure, the architecture, the BFMs and the VVCs. UVVM – Brand new features from the world’s #1 VHDL Verification MethodologyĪ good verification methodology could significantly reduce FPGA and ASIC development time.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |